A synchronous memory represented by a synchronous DRAM (Synchronous Dynamic Random Access Memory) is widely used for a main memory or the like of a personal computer. Because the synchronous memory can input and output data in synchronism with a clock signal supplied from a memory controller, when a higher-speed clock is used, a data transfer rate can be increased.
However, so long as a DRAM core performs an analog operation also in the synchronous DRAM, a considerably weak charge needs to be amplified based on a sense operation. Accordingly, it is not possible to shorten a time from issuing a read command until outputting first data. After a lapse of a predetermined delay time since issuance of the read command, the first data is outputted in synchronism with an external clock.
This delay time is generally called a “CAS latency” and is set to an integral multiple of a clock cycle. For example, when the CAS latency is 5 (CL=5), after fetching the read command in synchronism with the external clock, the first data is outputted in synchronism with the external clock after five cycles. That is, the first data is outputted after a lapse of the five clock cycles. A counter that counts such a latency is called a “latency counter”.
For the latency counter, there has been known a circuit described in “A 1.2 Gb/s/pin Double Data Rate SDRAM with On-Die-Termination”, Ho Young Song and 15 others, ISSCC 2003/SESSION 17/SRAM AND DRAM/PAPER 17.8, (United States), IEEE, 2003, p. 314. The latency counter described in the above non-patent document includes: a plurality of latch circuits that latch a read command; a switch that reads the read command from any one of the latch circuits; a first ring counter that selects the latch circuit to which the read command is latched by sequentially circulating the latch circuits; and a second ring counter that selects the latch circuit from which the read command is read by sequentially circulating the latch circuits. Thereby, the latched read command is outputted at a timing corresponding to a difference between a count value of the first ring counter and that of the second ring counter.
However, when different ring counters, i.e., one for input and the other for output, are used, if a frequency of a clock becomes high, synchronizing operations of the two ring counters become difficult. It sometimes becomes also impossible to simultaneously reset the two ring counters at a reset time. Accordingly, there arises a problem in that a count number of the latency is deviated, resulting in a malfunction.
To solve such a problem, the present inventor has proposed a method for sharing the ring counter between the uses, i.e., an input use and an output use. In this method, a value of the ring counter is used as a value for outputting, and that which is obtained by deviating the value of the ring counter by a predetermined value is used for inputting. Thereby, sharing the ring counter can be made.
However, as a result of further researches by the inventor, it was found that the ring counter itself probably malfunctioned in some cases. That is, the ring counter has a configuration such that out of the latch circuits connected in circulation, an active level (high level, for example) is latched to any one of the latch circuits, and the active level is shifted in circulation. However, at a time of entering a self-refresh mode or a power-down mode, a hazard is sometimes outputted to an internal clock depending on a certain timing. As a result, the ring counter can be in an unstable state.
When the ring counter is in an unstable state, an error occurs that the active level is latched to a plurality of latch circuits or a non-active level is latched to all the latch circuits. Such an error cannot be removed until when the entire memory is restarted. Accordingly, the latency counter cannot perform a normal operation any more without restarted.